1. Field of Invention
The present invention generally relates to a transient voltage suppressor.
2. Description of Prior Art
Along with the rapid development of science and technology at the present, integrated circuits are widely used in an electronic apparatus. A person skilled in the art knows that Electrostatic discharge (ESD) is one of main problems for the integrated circuits. Circuits of the integrated circuit may be reset or even damaged under ESD events. Currently, all consumer electronics are expected to pass the ESD test requirement of IEC 61000-4-2 standard by applying suitable protection scheme on the consumer electronics.
Referring to FIG. 1A and FIG. 1B, wherein FIG. 1A and FIG. 1B are block diagrams of an electronic apparatus which working in different modes. In FIG. 1A, a transient voltage suppressor 100 (TVS) is coupled to the circuit to be protected 120 in parallel. The circuit to be protected 120 is working in normal mode, and voltage levels of the operating voltage VPP and reference ground GND respectively keep in normal ranges. The TVS 110 sense the voltage levels of the operating voltage VPP and reference ground GND, and provides a high impendence between the operating voltage VPP and reference ground GND. Such as that, a current IOP can be provided to the circuit to be protected 120 for operating.
On the other hand, when a ESD event occurs, referring to FIG. 1B, the TVS 110 sense the voltage levels of the operating voltage VPP and reference ground GND, and provides a very low impendence between the operating voltage VPP and reference ground GND. Such as that, a current IESD caused by the ESD event can be discharged to the reference ground GND, and the circuit to be protected 120 is protected from damaged by the current IESD.